The design of integrated circuits in a time-efficient and cost-effective manner is critical to the integrated circuit (IC) industry. An integrated circuit needs to be small or have a dense packing density in order to produce more ICs per wafer and maximize profits. Unfortunately, a dense integrated circuit is designed with small transistors. These small transistors have small aspect ratios which result in slow switching speeds and propagation speeds of signals in the dense circuit. Therefore, the area of a circuit is traded off for speed. It is important to use a design process wherein specified or required speed constraints are met while size is not grossly impacted. In addition, this design process should be quick and easy to use.
Most of the methods for attaining speed critical circuits at a minimal circuit surface area use a custom design process. In a custom design process no library-stored gates are used. If a logic gate is required for a design, all of these logic gates are formed with the same default logic gate. For example, all ORs in an initial design are all the same logic gate size, strength, etc.. A program or designer then automatically/manually changes specific sizes of specific transistors along circuits paths in order to arrive at required circuit speeds. Since individual transistors are increased in size (which is the smallest circuit element in the design), a very small area (near optimal area) is achieved while speed constraints are adhered to. The problem is that each gate may be different from all others in that each transistor in the circuit is subject to size changes independent of what gate the transistor belongs to. Therefore, the changing of transistor sizes in a random and non-uniform manner to the gates results in all or many OR gates now being radically different from one another. This makes integration difficult and makes layout a nearly all-manual task. No gates can be stored and read from a library and the speed and efficiency of semi-custom design flow process is lost.
A process and apparatus is needed to improve circuit speed while arriving at a near-optimal area. This process and apparatus needs to be compatibility to a semi-custom design flow which uses library defined gates in order to maintain short time to market, easier layout processing, and efficiency, while attaining the benefits of the optimized speed at an optimal area.